This invention relates to a semiconductor memory using MOS transistors, and more particularly to a structure of a random access memory cell for dynamic operation which is suitable for large scale integration.
Two types of random access memory cell have been used for dynamic operation.
The first is the 3-transistor memory cell shown in FIG. 1, the three transistors T.sub.1, T.sub.2 and T.sub.3 together forming one bit. The transistor T.sub.1 has a write (W: write address) function, the transistor T.sub.3 has a read-out (R: read address) function and the transistor T.sub.2 has an amplification function. Data is stored in the form of an electric charge at the diffusion layer capacitance of T.sub.1 and the gate capacitance of T.sub.2. The charge can be held by periodic refreshing. The characteristic feature of this cell is that non-destructive read-out of data is possible (Din: data input, Dout: data output), and the cell itself is equipped with the amplification function. However, the most crucial problem with this cell is that the cell area is relatively great because of the 3-transistor/bit construction. Therefore, this type of cell has few commercial applications for products having a memory capacity greater than 4K bits.
In place of the cell of the kind described above, the 1-transistor/1-capacitor memory cell shown in FIG. 2 has been used for MOS DRAM having a greater memory capacity. This structure is disclosed in U.S. Pat. No. 3,387,286. A transistor T has the function of write/read-out address and the data is stored in a capacitor C. Periodic refreshing is necessary in the same way as in the cell shown in FIG. 1. Since the structure of this cell is ultimately simplified as a random access memory cell, it can be said that the cell is suitable for large scale integration. However, since read-out of the data is destructive read-out and since the cell itself is not equipped with the amplification function, the charge-storing capacitance of C must be kept above a predetermined value in order to secure a stable operation.
The main factors that determine the lower limit of charge-storing capacitance are as follows:
(1) the ratio of charge-storing capacitance to data line capacitance (C.sub.S /C.sub.D); PA0 (2) generation of minority carrier due to the incidence of .alpha. particles; and PA0 (3) junction leakage. PA0 (1) The cell area is equal to or smaller than that of the afore-mentioned 1-transistor/1-capacitor cell of the existing technology for fine etching. PA0 (2) The components of the cell can be reduced as a whole, keeping pace with the progress of technology in fine etching which is expected in the future so that miniaturiazation techniques will continue to improve.
Due to these three limitations, reduction of the area of the charge-storing capacitance portion has not kept pace with the progress in the technology of processing involving very fine etching in the production of IC's; hence, miniaturization has become a serious problem.